It is necessary to suppress a gate leak current, and to decrease EOT (Equivalent Oxide Thickness) to develop a technological advance and microfabrication in transistors of semiconductor devices such as DRAM. Therefore, the semiconductor devices using high-dielectric constant materials (High-k materials) as a gate insulating film are developed (for example, refer to JP Patent Kokai Publication No. JP-P2011-14689A (Patent Literature 1) which corresponds to US2012/080756A1 and JP Patent Kokai Publication No. JP-P2011-49282A (Patent Literature 2)).
A semiconductor device which is described in Patent Literature 1 is provided with a high dielectric gate insulating film which is formed on a substrate and a metal gate electrode which is formed on the high dielectric gate insulating film, and a halogen segregates on a metal gate electrode side at an interface between the high dielectric gate insulating film and the metal gate electrode.
In a semiconductor device which is described in Patent Literature 2, a gate structure having a high dielectric constant film and a metal gate electrode is formed on a semiconductor substrate in a MONOS memory forming area and a MISFET area.